In semiconductor manufacturing, a semiconductor workpiece or wafer often undergoes many processing steps or stages before a completed die is formed. For example, ion implantation processes are performed on the semiconductor wafer in order to provide a specific doping of the semiconductor workpiece in specific regions, such as seen in source and drain regions of CMOS devices. As integrated circuit devices are scaled down, designers face a tradeoff between short channel effects, drain induced barrier lowering, and output conductance when implementing both short channel and long channel CMOS devices on the wafer. Greater source/drain pocket (PKT) doping to suppress short channel effects in short channel devices typically worsens drain induced barrier lowering and deleteriously increases output conductance in long channel devices, such as analog devices.